1. Field
Exemplary embodiments of the present invention relate to a memory device and a memory system including the same, and more particularly, to a repair-related technology.
2. Description of the Related Art
FIG. 1 is a diagram for explaining a repair operation in a conventional memory device (for example, a DRAM).
A memory device may include a plurality of memory banks and one of the memory banks is shown in FIG. 1. Referring to FIG. 1, the memory device includes a memory array 110 including a plurality of memory cells, a row circuit 120 for activating a word line selected by a row address R_ADD, and a column circuit 130 for accessing (reading or writing) data of a bit line selected by a column address C_ADD.
A row fuse circuit 140 stores a row address, which corresponds to a defective memory cell in the memory array 110 as a repair row address REPAIR_R_ADD. A row comparison unit 150 compares the repair row address REPAIR_R_ADD stored in the row fuse circuit 140 with a row address R_ADD inputted from the outside of the memory device. When the repair row address REPAIR_R_ADD coincides with the row address R_ADD, the row comparison unit 150 controls the row circuit 120 to activate a redundancy word line instead of a word line designated by the row address R_ADD. That is, a row (a word line) corresponding to the repair row address REPAIR_R_ADD stored in the row fuse circuit 140 is replaced with a redundancy row (a redundancy word line).
In FIG. 1, a signal RACT indicates a signal that is activated in response to an active command for activating a word line in the memory array 110, and is deactivated in response to a precharge command for deactivating a word line. A signal IRD indicates a read command, and a signal IWR indicates a write command.
In the conventional fuse circuit 140, laser fused are generally used. Laser fuses store ‘high’ or low′ data depending on whether the laser fuse has been cut. The programming of the laser fuse is possible in a wafer state of a semiconductor, but it is not possible to program the laser fuse after a semiconductor wafer is mounted in a package. Furthermore, it is not possible to design the laser fuse below a certain size due to limitations in decreasing the pitch length thereof.
In order to alleviate such issues, a memory device may include nonvolatile memory, such as an e-fuse array circuit, a NAND flash memory, a NOR flash memory, an MRAM (Magnetoresistive Random Access Memory), a STT-MRAM (Spin Transfer Torque Magnetoresistive Random Access Memory), a ReRAM (Resistive Random Access Memory), or a PC RAM (Phase Change Random Access Memory) as disclosed in U.S. Pat. Nos. 6,940,751, 6,777,757, 6,667,902, 7,173,851, and 7,269,047, and repair data (a repair address) may be stored in a nonvolatile memory.
FIG. 2 is a diagram illustrating a nonvolatile memory circuit used in a memory device in order to store repair data.
Referring to FIG. 2, the memory device includes a plurality of memory banks BK0 to BK3, registers 210_0 to 210_3 provided to the respective memory banks BK0 to BK3 to store repair data, and a nonvolatile memory circuit 201.
The nonvolatile memory circuit 201 is a substitute of the row fuse circuit 140 shown in FIG. 1. Repair data (that is, repair addresses) corresponding to all the memory banks BK0 to BK3 is stored in the nonvolatile memory circuit 201. The nonvolatile memory circuit 201 may include any one of nonvolatile memories such as an e-fuse array circuit, a NAND flash memory, a NOR flash memory, an MRAM (Magnetoresistive Random Access Memory), an STT-MRAM (Spin Transfer Torque Magnetoresistive Random Access Memory), a ReRAM (Resistive Random Access Memory), and a PC RAM (Phase Change Random Access Memory).
The registers 210_0 to 210_3 are provided to the respective memory banks BK0 to BK3 and store repair data of the respective memory banks BK0 to BK3. The register 210_0 stores repair data of the memory bank BK0, and the register 210_2 stores repair data of the memory bank BK2. The registers 210_0 to 210_3 include latch circuits, and may store repair data only when power has been supplied. Repair data to be stored in the registers 210_0 to 210_3 is received from the nonvolatile memory circuit 201.
The reason for transferring the repair data stored in the nonvolatile memory circuit 201 to the registers 210_0 to 210_3 and using the repair data stored in the registers 210_0 to 210_3, instead of directly using the repair data stored in the nonvolatile memory circuit 201, is as follows. Since the nonvolatile memory circuit 201 has an array form, it takes a predetermined time to call data stored therein. That is, it is not possible to immediately call data stored in the nonvolatile memory circuit 201, and it is not possible to perform a repair operation by directly using the data. Accordingly, a boot-up operation, in which the repair data stored in the nonvolatile memory circuit 201 is transmitted to and stored in the registers 210_0 to 210_3, is performed and then the repair operation is performed using the data stored in the registers 210_0 to 210_3.
When the row fuse circuit 140 including the laser fuse is replaced with the nonvolatile memory circuit 201 and the registers 210_0 to 210_3, it is possible to repair additional defects found after the wafer state. A technology in which defects found after the memory device is fabricated (for example, the memory device is sold as products) may be repaired by accessing the nonvolatile memory circuit 201, has been researched.